1. Technical Field
The present disclosure relates to multi-core integrated circuits and, more specifically, to a system and method for self-adjusting critical path timing of multi-core very-large-scale integration (VLSI) chips.
2. Discussion of Related Art
Very-large-scale integration (VLSI) is a process for creating modern complex integrated circuits that may contain thousands, millions, and often billions of transistor-based circuits on a single chip. Such chips may include microprocessors such as central processing units (CPUs) for computer systems, system-on-chip devices, digital signal processors, graphical processing units (GPUs) and the like.
A modern trend in microprocessor design is to utilize two or more independent cores within a single chip. Efficiency gains may then be achieved as each of the cores is able to independently process instructions. While today many commercially available multi-core microprocessors are dual-core or quad-core, microprocessors including substantially higher-order cores are also available or in development.
Many software applications are designed to divide instructions into multiple threads that may be processed in parallel by the multiple cores of the microprocessor. Such applications may be well suited for exploiting the potential of multi-core microprocessors. For many of these applications, the multiple cores may operate, to some extent, asynchronously, with each core responsible for processing its own threads. However, some other applications may be able to benefit from the multiple cores operating in synchronous. Synchronizing the timing of the multiple cores may be difficult, as subtle manufacturing variations within the multiple-cores may permit some cores to operate at different speeds. These differences in core speeds may result in distinct critical path timing for each core.